The present disclosure relates generally to semiconductor memory devices, and more particularly, to an internal voltage generating apparatus for a semiconductor memory device.
According to high integration of the DRAM, a number of net dies per wafer must be maximized. Thus, an area allocated as a peri region in each die is gradually decreased. When the area of the peri region is decreased, it is difficult to use general pads in the narrow die. Even if a number of the pads used in the peri region is decreased, a multi-chip product test of the DRAM must be normally executed.
In addition, expenses are increased because of an increased time required for testing products, and a number of test items that cannot be tested by a specific equipment is increased because of deterioration of the equipment. To solve the foregoing problems, the test time may be reduced by using the multi-chip test technique that increases a number of dies which can be tested at a time.
FIG. 1 is a block diagram illustrating a conventional internal voltage generating apparatus for executing the multi-chip test. The conventional internal voltage generating apparatus includes a reference voltage generator 1, a core voltage amplifying unit 2, a peri voltage amplifying unit 3, a core voltage driver 4, a peri voltage driver 5, a core voltage pad 6, a peri voltage pad 7, a core reference voltage pad 9 and a peri reference voltage pad 10. Here, an amplifier A1 of the core voltage amplifying unit 2 receives an initial reference voltage VR0 from the reference voltage generator 1 through its positive (+) terminal. The amplifier A1, which has its negative (xe2x88x92) terminal connected to a common node of resistors R2C and R1C, outputs a core reference voltage VREFC through its output terminal. An amplifier A2 of the peri voltage amplifying unit 3 receives the initial reference voltage VR0 from the reference voltage generator 1 through its positive (+) terminal. The amplifier A2, which has its negative (xe2x88x92) terminal connected to a common node of resistors R2P and R1P, outputs a peri reference voltage VREFP through its output terminal.
The core voltage driver 4 drives the core reference voltage VREFC from the core voltage amplifying unit 2 and outputs a core voltage VCORE to a core unit of a cell and peri unit 8. The peri voltage driver 5 drives the peri reference voltage VPERI from the peri voltage amplifying unit 3 and outputs the peri voltage VPERI to a peri unit of the cell and peri unit 8. The core voltage pad 6 is connected to an output terminal of the core voltage driver 4 and outputs a core voltage for forcing the core voltage VCORE. The peri voltage pad 7 is connected to an output terminal of the peri voltage driver 5 and outputs a peri voltage for forcing the peri voltage VPERI.
The core voltage and the peri voltage are forced by the core voltage pad 6 and the peri voltage pad 7. As a result, one can test the operation of the cell and peri unit 8 in response to variation of internal voltages as one method for testing device property on completed wafers. That is, the device property test can be executed by forcing levels of the core voltage VCORE being internally-generated for a DRAM core region and the peri voltage VPERI being internally-generated for a DRAM peri region. In the device property test, an internal voltage margin is checked by increasing or decreasing the level of the core voltage VCORE or the peri voltage VPERI.
In the case of the aforementioned multi-chip test, 8, 16 or more devices are tested at the same time. Here, a current driving unit of the test equipment for forcing the core voltage VCORE and the peri voltage VPERI cannot handle current consumption of 8, 16, or more devices. Accordingly, the core reference voltage pad 9 for forcing the level of the core reference voltage VREFC is additionally provided in input terminal of the core voltage driver 4 in the chip, and the peri reference voltage pad 10 for forcing the level of the peri reference voltage VREFP is additionally provided in input terminal of the peri voltage driver 5.
In the conventional internal voltage generating apparatus, however, the core reference voltage pad 9 and the peri reference voltage pad 10 become loads of the core reference voltage VREFC and the peri reference voltage VREFP in a normal operation. In addition, wires connected to the core reference voltage pad 9 and the peri reference voltage pad 10 are exposed to external noise, which may change the levels of the core reference voltage VREFC and the peri reference voltage VREFP.
An internal voltage generating apparatus for a semiconductor device is described herein. The disclosed apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM for cutting down expenses. Further, the disclosed apparatus is configured to overcome load or noise due to a pad during a normal operation by cutting (switching off) a fuse after a wafer level test.
In particular, the internal voltage generating apparatus for a semiconductor memory device includes a reference voltage generator configured to generate an initial reference voltage, an internal voltage supply circuit configured to generate a core voltage and a peri voltage by using the initial reference voltage, and a forcing circuit configured to force different level voltages for a test. The forcing circuit includes an initial reference voltage pad connected to an output terminal of the reference voltage generator to output a forced initial reference voltage for test, a core voltage pad connected to a core voltage output terminal of the internal voltage supply circuit to output a forced core voltage for a test, and a peri voltage pad connected to a peri voltage output terminal of the internal voltage supply circuit to output a forced peri voltage for a test.